Junior Weeks

02-15 FEBRUARY

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Design Verification Engineer

Basic information
Role
IT
Specialisation
Embedded Systems
Seniority
Mid level
Employment
Full Time
Location
Hybrid
Min Experience
Three to five years
Salary
Non-disclosure salary
Technologies
Python
SystemVerilog
UVM
Perl
PCIe
NVMe
DDR
About the job

Join Our SoC Team as a Design Verification Engineer (Location: Poland only)

SK hynix memory solutions Poland is seeking a skilled Design Verification Engineer to strengthen our System-on-Chip (SoC) team. This is an opportunity to work on the core technology that drives our next-generation memory and storage solutions.

Key Technical Requirements:

  • Verification Methodology: Strong, hands-on experience with modern verification flows, especially SystemVerilog and the UVM framework.

  • Test Environment Development: Proven ability to create robust, reusable test benches and develop comprehensive constrained-random test plans.

  • Coverage & Closure: Experience driving functional and code coverage closure to meet sign-off requirements.

  • Scripting: Proficiency in scripting languages such as Python or Perl for automation and flow enhancement.

  • Protocol Knowledge: Familiarity with industry standard high-speed protocols (PCIe, NVMe, DDR) is a significant asset.

Ready for a new technical challenge? Take the next step in your career and contribute to a global leader in memory innovation.

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